Electronic devices having semiconductor memory with interface enhancement layer
US10042559B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2017 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Jan 30, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an interface enhancement layer interposed between the tunnel barrier layer and the pinned layer, wherein the interface enhancement layer may include an Fe-rich first layer; a Co-rich second layer formed over the first layer; and a metal layer formed over the second layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.