Automatic resumption of suspended write operation upon completion of higher priority write operation in a memory device
US10042587B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 2017 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Mar 13, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device can include: a memory array comprising a plurality of memory cells; an interface configured to receive a suspend command and first and second write commands from a host, where the second write command is of higher priority and follows the first write command; a status register configured to store an automatic resume enable bit; a memory controller configured to suspend, in response to the suspend command, a first write operation that is executing the first write command on the memory array; the memory controller being configured to execute a second write operation on the memory array in response to the second write command; and the memory controller being configured to resume the first write operation upon completion of the second write operation in response to the automatic resume enable bit being set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.