Operation of a multi-slice processor implementing exception handling in a nested translation environment
US10042691B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2016 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Jul 21, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more translation caches, where operation includes: determining, at the load/store slice, a real address from a cache hit in the translation cache for an effective address for an instruction received at a load/store slice; determining, at the load/store slice, an error condition corresponding to an access of the real address; determining, at the load/store slice, a process type indicating a source of the instruction to be a guest process; and responsive to determining the error condition, initiating, in dependence upon the process type indicating a source of the instruction to be a guest process, an effective address translation corresponding to a cache miss in the translation cache for the effective address for the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.