Inventor · Pflugerville, TX, US

Dwain A. Hicks

30Patents
10h-index
25Co-inventors
75Inventor score

Filing activity: Aug 2, 1993 → Nov 4, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US5581734A Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity Physics 71 Expired
US5584013A Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache Physics 70 Expired
US6085291A System and method for selectively controlling fetching and prefetching of data to a processor Physics 46 Expired
US7302527B2 Systems and methods for executing load instructions that avoid order violations Physics 44 Expired
US5787478A Method and system for implementing a cache coherency mechanism for utilization within a non-inclusive cache memory hierarchy Physics 25 Expired
US5953351A Method and apparatus for indicating uncorrectable data errors Physics 23 Expired
US5694573A Shared L2 support for inclusion property in split L1 data and instruction caches Physics 23 Expired
US6202128A Method and system for pre-fetch cache interrogation using snoop port Physics 13 Expired
US6240487A Integrated cache buffers Physics 12 Expired
US10740248B2 Methods and systems for predicting virtual address Physics 10 Active
US6446170B1 Efficient store machine in cache based microprocessor Physics 9 Expired
US7302530B2 Method of updating cache state information where stores only read the cache state information upon entering the queue Physics 8 Expired
US10621106B1 Methods and systems for incorporating non-tree based address translation into a hierarchical translation lookaside buffer (TLB) Physics 6 Active
US5692151A High performance/low cost access hazard detection in pipelined cache controller using comparators with a width shorter than and independent of total width of memory address Physics 5 Expired
US7376816B2 Method and systems for executing load instructions that achieve sequential load consistency Physics 4 Expired
US7464242B2 Method of load/store dependencies detection with dynamically changing address length Physics 4 Expired
US11061810B2 Virtual cache mechanism for program break point register exception handling Physics 2 Active
US10649778B1 Performance optimized congruence class matching for multiple concurrent radix translations Physics 1 Active
US11221963B2 Methods and systems for incorporating non-tree based address translation into a hierarchical translation lookaside buffer (TLB) Physics 1 Active
US10915459B2 Methods and systems for optimized translation of a virtual address having multiple virtual address portions using multiple translation lookaside buffer (TLB) arrays for variable page sizes Physics 1 Active
US7769985B2 Load address dependency mechanism system and method in a high frequency, low power processor system Physics 1 Active
US7730290B2 Systems for executing load instructions that achieve sequential load consistency Physics 1 Active
US6298417A Pipelined cache memory deallocation and storeback Physics 1 Expired
US10042691B2 Operation of a multi-slice processor implementing exception handling in a nested translation environment Physics 0 Active
US10534715B2 Operation of a multi-slice processor implementing a unified page walk cache Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.