Light-weight cache coherence for data processors with limited data sharing
US10042762B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2016 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Sep 22, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a plurality of processors, local memories associated with a corresponding processor, and at least one inter-processor link. In response to a first processor performing a load or store operation on an address of a corresponding local memory that is not currently in the local cache, a local cache allocates a first cache line and encodes a local state with the first cache line. In response to a load operation from an address of a remote memory that is not currently in the local cache, the local cache allocates a second cache line and encodes a remote state with the second cache line. The first processor performs subsequent loads and stores on the first cache line in the local cache in response to the local state, and subsequent loads from the second cache line in the local cache in response to the remote state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.