Multilevel ferroelectric memory cell for an integrated circuit

US10043567B2 · kind B2 · utility

Assignee

• NAMLAB GGMBH · DE

Inventors

• Stefan Slesazeck · Dresden, DE
• Halid Mulaosmanovic · Dresden, DE

Key dates

• Filing date: Nov 27, 2017
• Grant date: Aug 7, 2018
• Expiry date: Nov 27, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/122
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated circuit includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric layer stack comprising at least one ferroelectric material oxide layer. Each of the ferroelectric material oxide layers includes a ferroelectric material that is at least partially in a ferroelectric state. The ferroelectric layer stack comprises at least two ferroelectric domains. Further, the voltage which is to applied to the layer stack to induce polarization reversal differs for the individual domains such that polarization reversal of individual domains or of a portion of the totality of ferroelectric domains within the ferroelectric material of can be attained.