Memory circuit capable of implementing calculation operations
US10043581B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2017 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | May 23, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit capable of implementing calculation operations, including: memory cells arranged in rows and in columns, each cell including: a data bit storage node, a read-out transistor connected by its gate to the storage node, and a selection transistor series-connected with the read-out transistor between a reference node and a conductive output track common to all the cells of a same column; and a control circuit configured to simultaneously activate the selection transistors of at least two cells of a same column of the circuit, and to read from the conductive output track of the column a value representative of the result of a logic operation having as operands the data of the two cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.