Jean-Philippe Noel
23Patents
5h-index
23Co-inventors
65Inventor score
Filing activity: Apr 29, 2008 → Dec 19, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8482070B1 | Silicon-on-insulator CMOS integrated circuit with multiple threshold voltages and a method for designing the same | Electricity | 19 | Active |
| US8969967B2 | Self-contained integrated circuit including adjacent cells of different types | Electricity | 9 | Active |
| US9092590B2 | Method for generating a topography of an FDSOI integrated circuit | Physics | 6 | Active |
| US9093499B2 | Integrated circuit using FDSOI technology, with well sharing and means for biasing oppositely doped ground planes present in a same well | Electricity | 5 | Active |
| US9479168B2 | Method for controlling an integrated circuit | Electricity | 5 | Active |
| US9000840B2 | Integrated circuit comprising a clock tree cell | Electricity | 4 | Active |
| US8311518B2 | Method and system for executing applications in wireless telecommunication networks | Electricity | 3 | Active |
| US10043581B2 | Memory circuit capable of implementing calculation operations | Physics | 3 | Active |
| US10872642B2 | System comprising a memory capable of implementing calculation operations | Electricity | 1 | Active |
| US10910040B2 | Memory circuit | Physics | 1 | Active |
| US9136366B2 | Transistor with coupled gate and ground plane | Electricity | 1 | Active |
| US8937505B2 | Integrated circuit comprising a clock tree cell | Electricity | 1 | Active |
| US9911737B2 | Integrated circuit comprising transistors with different threshold voltages | Electricity | 0 | Active |
| US11043248B2 | Circuit for detection of predominant data in a memory cell | Physics | 0 | Active |
| US10803927B2 | Partitioned memory circuit capable of implementing calculation operations | Physics | 0 | Active |
| US11031076B2 | Memory circuit capable of implementing calculation operations | Physics | 0 | Active |
| US10297319B2 | Memory device with unipolar resistive memory cells with programmable resistive element end control transistor and set/reset operations of thereof | Physics | 0 | Active |
| US10811087B2 | Memory circuit capable of implementing calculation operations | Physics | 0 | Active |
| US12362011B2 | SRAM with reconfigurable setting | Physics | 0 | Active |
| US11875848B2 | Buffer memory adapted to implment calculations having operands as data | Physics | 0 | Active |
| US10847216B2 | SRAM memory having a reduced leakage current | Physics | 0 | Active |
| US12393705B2 | Direct data transfer system | Physics | 0 | Active |
| US8723267B2 | Integrated circuit made out of SOI with transistors having distinct threshold voltages | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.