Mitigating pattern collapse
US10043706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2013 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Aug 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.