Inventor · Huoshaolun, TW

Ya-Lien Lee

47Patents
4h-index
42Co-inventors
59Inventor score

Filing activity: Aug 31, 2012 → Aug 2, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8736056B2 Device for reducing contact resistance of a metal Electricity 390 Active
US8962473B2 Method of forming hybrid diffusion barrier layer and semiconductor device thereof Electricity 10 Active
US10312098B2 Method of forming an interconnect structure Electricity 5 Active
US10163644B2 Interconnect structure including a conductive feature and a barrier layer on sidewalls and a bottom surface of the conductive feature and method of forming the same Electricity 4 Active
US9659856B2 Two step metallization formation Electricity 3 Active
US9209072B2 Global dielectric and barrier layer Electricity 2 Active
US9214383B2 Method of semiconductor integrated circuit fabrication Electricity 2 Active
US10079176B2 Method of using a barrier-seed tool for forming fine pitched metal interconnects Electricity 2 Active
US9159666B2 Device and method for reducing contact resistance of a metal Electricity 1 Active
US9892963B2 Device and method for reducing contact resistance of a metal Electricity 1 Active
US11398406B2 Selective deposition of metal barrier in damascene processes Electricity 1 Active
US9941199B2 Two step metallization formation Electricity 1 Active
US11676898B2 Diffusion barrier for semiconductor device and method Electricity 1 Active
US10867800B2 Method of forming an interconnect structure having a carbon-containing barrier layer Electricity 1 Active
US10354914B2 Global dielectric and barrier layer Electricity 1 Active
US9818834B2 Semiconductor device structure and method for forming the same Electricity 1 Active
US10043706B2 Mitigating pattern collapse Electricity 1 Active
US9812397B2 Method of forming hybrid diffusion barrier layer and semiconductor device thereof Electricity 0 Active
US10672652B2 Gradient atomic layer deposition Electricity 0 Active
US10163719B2 Method of forming self-alignment contact Electricity 0 Active
US11851749B2 Semiconductor device, method and machine of manufacture Electricity 0 Active
US11742291B2 Diffusion barrier layer for conductive via to decrease contact resistance Electricity 0 Active
US11810857B2 Via for semiconductor device and method Electricity 0 Active
US11145542B2 Global dielectric and barrier layer Electricity 0 Active
US10950495B2 Mitigating pattern collapse Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.