Method for testing semiconductor wafers using temporary sacrificial bond pads
US10043722B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 24, 2014 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Dec 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/94
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for testing a semiconductor wafer, including individual semiconductor devices located on the semiconductor wafer, using temporary counterpart sacrificial bond pads. The method includes arranging individual semiconductor devices on the semiconductor wafer in a configuration having horizontal rows of the individual semiconductor devices separated by functional horizontal scribe lanes, and having vertical columns of individual semiconductor devices separated by functional vertical scribe lanes. The method includes creating the temporary counterpart sacrificial bond pads, located in the functional horizontal scribe lanes and/or vertical scribe lanes, that are electrically connected to corresponding normal individual bond pads located on individual semiconductor devices. The method also includes electrically testing the individual semiconductor devices using the temporary counterpart sacrificial bond pads, and destroying the temporary counterpart sacrificial bond pads upon completion of the electrical testing when the individual semiconductor devices are cut from the semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.