Patent · US Active

Buried interconnect for semiconductor circuits

US10043798B2 · kind B2 · utility

0Cited by

6References

13Claims

0Family size

Assignee

IMEC VZW · BE

Inventors

Stefan Cosemans · Mol, BE
Praveen Raghavan · Leefdaal, BE
Steven Demuynck · Aarschot, BE
Julien Ryckaert · Schaerbeek - Schaarbeek, BE

Key dates

Filing date	Aug 25, 2016
Grant date	Aug 7, 2018
Priority date	—
Expiry date	Aug 25, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/83
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor circuit comprises a Front End of Line (FEOL) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the FEOL and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.