Julien Ryckaert
30Patents
5h-index
34Co-inventors
65Inventor score
Filing activity: Aug 22, 2005 → Dec 19, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10636739B2 | Integrated circuit chip with power delivery network on the backside of the chip | Electricity | 43 | Active |
| US10403627B2 | Memory device for a dynamic random access memory | Electricity | 9 | Active |
| US8094051B2 | Sigma-delta-based analog-to-digital converter | Electricity | 6 | Active |
| US9678142B2 | Two-step interconnect testing of semiconductor dies | Electricity | 5 | Active |
| US10332588B2 | Static random access memory device having interconnected stacks of transistors | Electricity | 5 | Active |
| US10242907B2 | Method for interrupting a line in an interconnect | Electricity | 5 | Active |
| US7719373B2 | Device and method for generating a signal with predefined transcient at start-up | Electricity | 4 | Active |
| US10720363B2 | Method of forming vertical transistor device | Electricity | 4 | Active |
| US10607896B2 | Method of forming gate of semiconductor device and semiconductor device having same | Electricity | 4 | Active |
| US11164942B1 | Method for forming nanosheet transistor structures | Electricity | 4 | Active |
| US11244949B2 | Semiconductor device having stacked transistor pairs and method of forming same | Electricity | 3 | Active |
| US11018235B2 | Vertically stacked semiconductor devices having vertical channel transistors | Electricity | 2 | Active |
| US7822097B2 | Devices and methods for ultra-wideband communications | Electricity | 1 | Active |
| US11515399B2 | Self-aligned contacts for walled nanosheet and forksheet field effect transistor devices | Electricity | 1 | Active |
| US12424276B2 | Multiport memory cells including stacked active layers | Electricity | 0 | Active |
| US11201093B2 | Method of manufacturing a semiconductor device including the horizontal channel FET and the vertical channel FET | Electricity | 0 | Active |
| US11381242B2 | 3D integrated circuit | Electricity | 0 | Active |
| US11211404B2 | Memory devices based on ferroelectric field effect transistors | Electricity | 0 | Active |
| US10833161B2 | Semiconductor device and method | Electricity | 0 | Active |
| US11335597B2 | Method for forming a buried metal line | Electricity | 0 | Active |
| US11462443B2 | Self-aligned contacts for nanosheet field effect transistor devices | Electricity | 0 | Active |
| US11677401B2 | 3D integrated count | Electricity | 0 | Active |
| US10748815B2 | Three-dimensional semiconductor device and method of manufacturing same | Electricity | 0 | Active |
| US10460067B2 | Method of patterning target layer | Electricity | 0 | Active |
| US10522552B2 | Method of fabricating vertical transistor device | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.