Edge based partial response equalization
US10044530B2 · kind B2 · utility
3Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2016 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Jun 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03617
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) memory controller includes receiver circuitry to receive read data from a memory. The receiver circuitry includes equalization circuitry having at least one tap to apply data level equalization to the read data, and a tap weight adapter circuit. The tap weight adapter circuit adaptively generates a data level tap weight corresponding to the data level equalization from an edge analysis of previously received read data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.