Inventor · San Francisco, CA, US

Brian S. Leibowitz

155Patents

16h-index

71Co-inventors

85Inventor score

Filing activity: Jan 20, 2006 → Jan 26, 2024

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8588280B2	Asymmetric communication on shared links	Emerging Cross-Sectional Technologies	141	Active
US8279976B2	Signaling with superimposed differential-mode and common-mode signals	Electricity	80	Active
US9565036B2	Techniques for adjusting clock signals to compensate for noise	Electricity	59	Active
US8929496B2	Receiver with enhanced clock and data recovery	Electricity	56	Active
US8824222B2	Fast-wake memory	Physics	36	Active
US9117496B2	Memory device comprising programmable command-and-address and/or data interfaces	Electricity	26	Active
US9046909B2	On-chip regulator with variable load compensation	Physics	24	Active
US7949041B2	Methods and circuits for asymmetric distribution of channel equalization between devices	Electricity	22	Active
US8198930B2	Reducing power-supply-induced jitter in a clock-distribution circuit	Electricity	21	Active
US8824224B2	Frequency-agile strobe window generation	Electricity	21	Active
US8836394B2	Method and apparatus for source-synchronous signaling	Electricity	18	Active
US9563597B2	High capacity memory systems with inter-rank skew tolerance	Electricity	17	Active
US8548110B2	Receiver with clock recovery circuit and adaptive sample and equalizer timing	Electricity	17	Active
US8311176B2	Clock and data recovery employing piece-wise estimation on the derivative of the frequency	Electricity	16	Active
US9304579B2	Fast-wake memory control	Physics	16	Active
US8989249B2	High-speed signaling systems with adaptable pre-emphasis and equalization	Emerging Cross-Sectional Technologies	16	Active
US8289032B2	Integrated circuit having receiver jitter tolerance (“JTOL”) measurement	Physics	14	Active
US8804397B2	Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator	Electricity	14	Active
US8941420B2	Low-latency, frequency-agile clock multiplier	Electricity	13	Active
US9768947B2	Clock and data recovery having shared clock generator	Electricity	13	Active
US8766647B2	Method and apparatus for power sequence timing to mitigate supply resonance in power distribution network	Physics	11	Active
US9843315B2	Data transmission using delayed timing signals	Physics	10	Active
US9569308B1	Reduced-overhead error detection and correction	Electricity	10	Active
US7590175B2	DFE margin test methods and circuits that decouple sample and feedback timing	Electricity	9	Active
US9818463B2	Memory control component with inter-rank skew tolerance	Electricity	8	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.