Method and device for testing a chain of flip-flops
US10048317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2016 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Aug 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318566
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.