Flushing control within a multi-threaded processor
US10049043B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 12, 2016 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Oct 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus 2 performs multi-threaded processing using the processing pipeline 6, 8, 10, 12, 14, 16, 18. Flush control circuitry 30 is responsive to multiple different types of flush trigger. Different types of flush trigger result in different sets of state being flushed for the thread which resulted in the flush trigger with state for other thread not being flushed. For example, a relatively low latency stall may result in flushing back to a first flush point whereas a longer latency stall results in flushing back to a second flush point and the loss of more state data. The data flushed back to the first flushed point may be a subset of the data flushed back to the second flush point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.