Peter Richard Greenhalgh
33Patents
5h-index
27Co-inventors
65Inventor score
Filing activity: Jan 23, 2008 → Apr 7, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10394716B1 | Apparatus and method for controlling allocation of data into a cache storage | Physics | 30 | Active |
| US8533505B2 | Data processing apparatus and method for transferring workload between source and destination processing circuitry | Emerging Cross-Sectional Technologies | 10 | Active |
| US10613869B2 | Branch target address provision | Physics | 10 | Active |
| US7925866B2 | Data processing apparatus and method for handling instructions to be executed by processing circuitry | Physics | 9 | Active |
| US8418187B2 | Virtualization software migrating workload between processing circuitries while making architectural states available transparent to operating system | Emerging Cross-Sectional Technologies | 5 | Active |
| US9477479B2 | Instruction prefetch throttling using instruction count and branch prediction | Physics | 5 | Active |
| US8347067B2 | Instruction pre-decoding of multiple instruction sets | Physics | 4 | Active |
| US8635406B2 | Data processing apparatus and method for providing target address information for branch instructions | Physics | 3 | Active |
| US9286222B2 | Data processing apparatus and method for transferring workload between source and destination processing circuitry | Emerging Cross-Sectional Technologies | 2 | Active |
| US10049043B2 | Flushing control within a multi-threaded processor | Physics | 2 | Active |
| US7831815B2 | Data processing apparatus and method for identifying sequences of instructions | Physics | 2 | Active |
| US7917735B2 | Data processing apparatus and method for pre-decoding instructions | Physics | 1 | Active |
| US10705587B2 | Mode switching in dependence upon a number of active threads | Emerging Cross-Sectional Technologies | 1 | Active |
| US11340901B2 | Apparatus and method for controlling allocation of instructions into an instruction cache storage | Physics | 1 | Active |
| US7747839B2 | Data processing apparatus and method for handling instructions to be executed by processing circuitry | Physics | 0 | Active |
| US10095518B2 | Allowing deletion of a dispatched instruction from an instruction queue when sufficient processor resources are predicted for that instruction | Physics | 0 | Active |
| US7925867B2 | Pre-decode checking for pre-decoded instructions that cross cache line boundaries | Physics | 0 | Active |
| US11803388B2 | Apparatus and method for predicting source operand values and optimized processing of instructions | Physics | 0 | Active |
| US9213547B2 | Processor and method for processing instructions using at least one processing pipeline | Physics | 0 | Active |
| US11074080B2 | Apparatus and branch prediction circuitry having first and second branch prediction schemes, and method | Physics | 0 | Active |
| US12182261B2 | Controlling use of data determined by a resolve-pending speculative operation | Physics | 0 | Active |
| US9952871B2 | Controlling execution of instructions for a processing pipeline having first out-of order execution circuitry and second execution circuitry | Physics | 0 | Active |
| US10402203B2 | Determining a predicted behaviour for processing of instructions | Physics | 0 | Active |
| US11397584B2 | Tracking speculative data caching | Physics | 0 | Active |
| US9075622B2 | Reducing errors in pre-decode caches | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.