Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US10049953B2 · kind B2 · utility
13Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2016 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Jan 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.