Inventor · Hsinchu, TW

Tin-Hao Kuo

230Patents
12h-index
87Co-inventors
85Inventor score

Filing activity: Feb 11, 2010 → Jan 24, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US8922005B2 Methods and apparatus for package on package devices with reversed stud bump through via interconnections Emerging Cross-Sectional Technologies 57 Active
US9449941B2 Connecting function chips to a package to form package-on-package Electricity 45 Active
US10269773B1 Semiconductor packages and methods of forming the same Electricity 38 Active
US8288871B1 Reduced-stress bump-on-trace (BOT) structures Electricity 37 Active
US8853853B2 Bump structures Emerging Cross-Sectional Technologies 21 Active
US8318596B2 Pillar structure having a non-planar surface for semiconductor devices Electricity 18 Active
US9105530B2 Conductive contacts having varying widths and method of manufacturing same Emerging Cross-Sectional Technologies 18 Active
US9425136B2 Conical-shaped or tier-shaped pillar connections Electricity 17 Active
US10128213B2 Integrated fan-out stacked package with fan-out redistribution layer (RDL) Electricity 14 Active
US10049953B2 Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors Electricity 13 Active
US9917072B2 Method of manufacturing an integrated stacked package with a fan-out redistribution layer (RDL) and a same encapsulating process Electricity 12 Active
US8803319B2 Pillar structure having a non-planar surface for semiconductor devices Electricity 12 Active
US8546945B2 Pillar structure having a non-planar surface for semiconductor devices Electricity 11 Active
US9190348B2 Scheme for connector site spacing and resulting structures Electricity 8 Active
US9646923B2 Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices Electricity 8 Active
US10978382B2 Integrated circuit package and method Electricity 8 Active
US9287234B2 Dummy flip chip bumps for reducing stress Electricity 8 Active
US11004803B2 Dummy dies for reducing warpage in packages Electricity 7 Active
US11508656B2 Semiconductor package and method Electricity 7 Active
US9105533B2 Bump structure having a single side recess Emerging Cross-Sectional Technologies 7 Active
US8970033B2 Extending metal traces in bump-on-trace structures Electricity 7 Active
US10490468B2 Semiconductor structure with conductive structure Electricity 6 Active
US10128195B2 Substrate design with balanced metal and solder resist density Electricity 6 Active
US8921222B2 Pillar structure having a non-planar surface for semiconductor devices Electricity 6 Active
US9871013B2 Contact area design for solder bonding Emerging Cross-Sectional Technologies 6 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.