Metal silicate spacers for fully aligned vias
US10049974B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2016 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Aug 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-level semiconductor device and a method of fabricating a multi-level semiconductor device involve a first interlayer dielectric (ILD) layer with one or more metal lines formed therein. A silicide is formed on a surface of the first ILD layer and is directly adjacent to each of the one or more metal lines on both sides of each of the one or more metal lines. A second ILD is formed above the silicide, and a via is formed through the second ILD above one of the one or more metal lines. One or more second metal lines are formed above the second ILD, one of which is formed in the via. The second metal line in the via contacts the one of the one or more metal lines and the silicide adjacent to the one of the one or more metal lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.