Packaging device and method of making the same
US10050001B2 · kind B2 · utility
0Cited by
14References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2016 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Sep 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an integrated chip packaging device. In some embodiments, the packaging device has a first package component. A metal trace is arranged on a surface of the first package component. The metal trace has an undercut. A molding material fills the undercut of the metal trace and has a sloped outermost sidewall with a height that monotonically decreases from a position below a top surface of the metal trace to the surface of the first package component. A solder region is arranged over the metal trace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.