Quilt packaging system with mated metal interconnect nodules and voids
US10050027B2 · kind B2 · utility
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3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Mar 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/175
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
First and second integrated devices each have an optical component and a plurality of interconnect structures disposed one edge thereon. The first edge surface of the second integrated device is positioned contiguous to the first edge surface of the first integrated device. The interconnect structures disposed on the first integrated device are in physical contact with the interconnect structures disposed on the edge surface of the second integrated device so as to provide alignment for conveying at least one signal between the optical components on the first and second integrated devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.