SRAM cell and logic cell design
US10050042B2 · kind B2 · utility
11Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2016 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Jul 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.