Circuit for level shifting a clock signal using a voltage multiplier
US10050524B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 1, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Nov 1, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.