Vikas Rana
51Patents
6h-index
23Co-inventors
68Inventor score
Filing activity: Dec 24, 2008 → Feb 27, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9755621B1 | Single stage cascoded voltage level shifting circuit | Electricity | 11 | Active |
| US9634562B1 | Voltage doubling circuit and charge pump applications for the voltage doubling circuit | Electricity | 9 | Active |
| US9466347B1 | Row decoder for non-volatile memory devices and related methods | Physics | 8 | Active |
| US9325323B2 | CMOS oscillator having stable frequency with process, temperature, and voltage variation | Electricity | 7 | Active |
| US10050524B1 | Circuit for level shifting a clock signal using a voltage multiplier | Emerging Cross-Sectional Technologies | 7 | Active |
| US8461899B2 | Negative voltage level shifter circuit | Electricity | 7 | Active |
| US10811960B2 | Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation | Electricity | 4 | Active |
| US9159425B2 | Non-volatile memory with reduced sub-threshold leakage during program and erase operations | Physics | 4 | Active |
| US10461636B2 | Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation | Electricity | 3 | Active |
| US10250133B2 | Single-stage CMOS-based voltage quadrupler circuit | Electricity | 3 | Active |
| US11031865B2 | Charge pump circuit configured for positive and negative voltage generation | Electricity | 2 | Active |
| US11070128B2 | Charge pump regulation circuit to increase program and erase efficiency in nonvolatile memory | Physics | 2 | Active |
| US11424676B2 | Positive and negative charge pump control | Electricity | 2 | Active |
| US7750689B1 | High voltage switch with reduced voltage stress at output stage | Electricity | 2 | Active |
| US9659933B2 | Body bias multiplexer for stress-free transmission of positive and negative supplies | Electricity | 2 | Active |
| US9613696B1 | Memory device including decoder for a program pulse and related methods | Physics | 1 | Active |
| US10658364B2 | Method for converting a floating gate non-volatile memory cell to a read-only memory cell and circuit structure thereof | Electricity | 1 | Active |
| US10127990B1 | Non-volatile memory (NVM) with dummy rows supporting memory operations | Physics | 1 | Active |
| US10333397B2 | Multi-stage charge pump circuit operating to simultaneously generate both a positive voltage and a negative voltage | Electricity | 1 | Active |
| US11615820B1 | Regulator of a sense amplifier | Physics | 1 | Active |
| US10211727B1 | Circuit for level shifting a clock signal using a voltage multiplier | Emerging Cross-Sectional Technologies | 1 | Active |
| US7919983B1 | Multiple output level shifter | Electricity | 1 | Active |
| US11665915B2 | Method for converting a floating gate non-volatile memory cell to a read-only memory cell and circuit structure thereof | Electricity | 0 | Active |
| US11863066B2 | Positive and negative charge pump control | Electricity | 0 | Active |
| US11342031B2 | Circuit and method for process and temperature compensated read voltage for non-volatile memory | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.