Polyphase decimation FIR filters and methods
US10050607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2014 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Jun 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2017/0245
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.