Ankur Bal
58Patents
4h-index
24Co-inventors
66Inventor score
Filing activity: Feb 7, 2002 → Apr 14, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6748577B2 | System for simplifying the programmable memory to logic interface in FPGA | Electricity | 43 | Expired |
| US9379728B1 | Self-calibrated digital-to-analog converter | Electricity | 11 | Active |
| US8159381B2 | Glitch free dynamic element matching scheme | Electricity | 8 | Active |
| US10050640B1 | High speed data weighted averaging architecture | Electricity | 6 | Active |
| US6888374B2 | FPGA peripheral routing with symmetric edge termination at FPGA boundaries | Electricity | 4 | Expired |
| US6646465B2 | Programmable logic device including bi-directional shift register | Electricity | 4 | Expired |
| US10218380B1 | High speed data weighted averaging architecture | Electricity | 4 | Active |
| US9780803B1 | Apparatus for built-in self-test (BIST) of a Nyquist rate analog-to-digital converter (ADC) circuit | Electricity | 3 | Active |
| US9015219B2 | Apparatus for signal processing | Electricity | 3 | Active |
| US6642743B2 | System for rapid configuration of a programmable logic device | Electricity | 3 | Expired |
| US8645445B2 | Filter block for compensating droop in a frequency response of a signal | Electricity | 2 | Active |
| US6624771B2 | Concurrent logic operations using decoder circuitry of a look-up table | Electricity | 2 | Expired |
| US10211850B1 | High speed data weighted averaging architecture | Electricity | 2 | Active |
| US9246509B1 | Methods and apparatus for offline mismatch removal in sigma delta analog-to-digital converters | Electricity | 2 | Active |
| US7038489B2 | Method for sharing configuration data for high logic density on chip | Electricity | 2 | Expired |
| US8731214B2 | Noise removal system | Electricity | 2 | Active |
| US11656848B2 | High throughput parallel architecture for recursive sinusoid synthesizer | Electricity | 1 | Active |
| US10050607B2 | Polyphase decimation FIR filters and methods | Electricity | 1 | Active |
| US10862503B2 | Clock jitter measurement using signal-to-noise ratio degradation in a continuous time delta-sigma modulator | Electricity | 1 | Active |
| US9225321B2 | Signal synchronizing systems and methods | Physics | 1 | Active |
| US8803718B2 | Glitch free dynamic element matching scheme | Electricity | 1 | Active |
| US11522553B2 | Sigma-delta analog-to-digital converter circuit with real time correction for digital-to-analog converter mismatch error | Electricity | 1 | Active |
| US11094354B2 | First order memory-less dynamic element matching technique | Electricity | 1 | Active |
| US7030648B2 | High performance interconnect architecture for field programmable gate arrays | Electricity | 1 | Expired |
| US11043960B2 | Sigma-delta analog-to-digital converter circuit with correction for mismatch error introduced by the feedback digital-to-analog converter | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.