Clock and data recovery having shared clock generator
US10050771B2 · kind B2 · utility
4Cited by
31References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Aug 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0067
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.