Division operations for memory
US10055196B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2016 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Sep 3, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5353
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first address space comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space stores a dividend value. A second address space comprises a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space stores a divisor value. A third address space comprises a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space stores a remainder value. Sensing circuitry can be configured to receive the dividend value and the divisor value, divide the dividend value by the divisor value, and store a remainder result in the third number of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.