Hardware-based atomic operations for supporting inter-task communication
US10055342B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2014 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Sep 12, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/546
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure describes techniques for supporting inter-task communication in a parallel computing system. The techniques for supporting inter-task communication may use hardware-based atomic operations to maintain the state of a pipe. A pipe may refer to a First-In, First-Out (FIFO)-organized buffer that allows various tasks to interact with the buffer as data producers or data consumers. Various pipe implementations may use multiple state parameters to define the state of a pipe. The hardware-based atomic operations described in this disclosure may modify multiple pipe state parameters in an atomic fashion. Modifying multiple pipe state parameters in an atomic fashion may avoid race conditions that would otherwise occur when multiple producers and/or multiple consumers attempt to modify the state of a pipe at the same time. In this way, pipe-based inter-task communication may be supported in a parallel computing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.