Visualization of analysis process parameters for layout-based checks
US10055533B2 · kind B2 · utility
1Cited by
11References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 2015 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | May 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and mechanisms for marking the parameters of a circuit analysis process for visual identification are disclosed. The visually-identified parameters can then be employed with the results of the circuit analysis to debug the layout design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.