Allocation of tiles to processing engines in a graphics processing system
US10055877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2016 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Dec 21, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/122
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics processing system processes primitive fragments using a rendering space which is sub-divided into tiles. The graphics processing system comprises processing engines configured to apply texturing and/or shading to primitive fragments. The graphics processing system also comprises a cache system for storing graphics data for primitive fragments, the cache system including multiple cache subsystems. Each of the cache subsystems is coupled to a respective set of one or more processing engines. The graphics processing system also comprises a tile allocation unit which operates in one or more allocation modes to allocate tiles to processing engines. The allocation mode(s) include a spatial allocation mode in which groups of spatially adjacent tiles are allocated to the processing engines according to a spatial allocation scheme, which ensures that each of the groups of spatially adjacent tiles is allocated to a set of processing engines which are coupled to the same cache subsystem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.