Substrate design for semiconductor packages and method of forming same
US10056267B2 · kind B2 · utility
6Cited by
83References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2014 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Apr 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.