Inventor · Tainan, TW

Tsung-Ding Wang

101Patents
12h-index
60Co-inventors
85Inventor score

Filing activity: Oct 28, 2008 → Dec 28, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US9496189B2 Stacked semiconductor devices and methods of forming same Electricity 1,637 Active
US9275924B2 Semiconductor package having a recess filled with a molding compound Electricity 59 Active
US9343433B2 Packages with stacked dies and methods of forming the same Electricity 26 Active
US8803332B2 Delamination resistance of stacked dies in die saw Electricity 26 Active
US9768145B2 Methods of forming multi-die package structures including redistribution layers Electricity 24 Active
US8823180B2 Package on package devices and methods of packaging semiconductor dies Electricity 20 Active
US8426256B2 Method of forming stacked-die packages Electricity 19 Active
US9564416B2 Package structures and methods of forming the same Electricity 18 Active
US10026671B2 Substrate design for semiconductor packages and method of forming same Electricity 16 Active
US11101209B2 Redistribution structures in semiconductor packages and methods of forming same Electricity 16 Active
US9059109B2 Package assembly and method of forming the same Electricity 12 Active
US9935090B2 Substrate design for semiconductor packages and method of forming same Electricity 12 Active
US10319607B2 Package-on-package structure with organic interposer Electricity 11 Active
US9355933B2 Cooling channels in 3DIC stacks Electricity 9 Active
US8704354B2 Package on package structures and methods for forming the same Electricity 9 Active
US9653443B2 Thermal performance structure for semiconductor packages and method of forming same Electricity 9 Active
US8743561B2 Wafer-level molded structure for package assembly Electricity 7 Active
US10804242B2 Methods of forming multi-die package structures including redistribution layers Electricity 7 Active
US8658464B2 Mold chase design for package-on-package applications Electricity 7 Active
US7687311B1 Method for producing stackable dies Electricity 6 Active
US10056267B2 Substrate design for semiconductor packages and method of forming same Electricity 6 Active
US9006032B2 Package on package structures and methods for forming the same Electricity 6 Active
US9502383B2 3D integrated circuit package processing with panel type lid Electricity 6 Active
US8803323B2 Package structures and methods for forming the same Electricity 5 Active
US9437551B2 Concentric bump design for the alignment in die stacking Electricity 5 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.