Application of antiferroelectric like materials in non-volatile memory devices

US10056393B2 · kind B2 · utility

Assignee

• NAMLAB GGMBH · DE

Inventors

• Uwe Schroder · Dresden, DE
• Milan Pe{hacek over (s)}ić · San Jose, US

Key dates

• Filing date: Mar 1, 2016
• Grant date: Aug 21, 2018
• Expiry date: Apr 2, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2213/79
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Integrated devices comprising pinched hysteresis loop (PHL) materials in a capacitor or a transistor stack are disclosed. PHL materials include field induced ferroelectrics (FFE), anti-ferroelectric (AFE) and relaxor type ferroelectric (RFE) materials. Each integrated device includes a material stack with a PHL material layer disposed between two electrodes. Application of this material is dependent on inducing of an electric field bias over the stack. According to one option, electrodes having different workfunction values can be employed to induce the required built-in bias field and enable use of PHL materials. According to another option, a PHL material and charges, e.g., a charge interlayer, are disposed between two electrodes such that an induced built-in bias field appears. Integrated devices employing the PHL material stack include memories, transistors, and piezo- and pyroelectric devices.