Semiconductor memory devices having closely spaced bit lines
US10056404B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2016 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Jun 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
Abstract
The inventive concepts relate to a semiconductor memory device. The semiconductor memory device includes a substrate including a circuit region and first and second connection regions respectively disposed at both sides of the circuit region opposite to each other, a logic structure including a logic circuit disposed on the circuit region and a lower insulating layer covering the logic circuit, and a memory structure on the logic structure. The logic circuit includes a first page buffer disposed adjacently to the first connection region and a second page buffer disposed adjacently to the second connection region. The memory structure includes bit lines extending onto at least one of the first and second connection regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.