Semiconductor device and manufacturing method thereof
US10056405B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2016 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Aug 31, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/423
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the case where a signal delay is found in a circuit operation in a semiconductor chip, when a repeater for delay reduction is additionally formed as a result of a design change, an increase in the area of the semiconductor chip and an increase in the manufacturing cost of a semiconductor device are prevented. The inverter forming the repeater is formed of transistors formed in the upper portion of stacked wiring layers, not transistors in the vicinity of a main surface of a semiconductor substrate. By thus implementing a design change such that the repeater is added, the number of the wiring layers which need a layout change is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.