Method for manufacturing vertical super junction drift layer of power semiconductor devices

US10056452B2 · kind B2 · utility

Assignees

• University of Electronic Science and Technology of China · CN
• ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC · CN

Inventors

• Zehong Li · Chengdu, CN
• Wenlong SONG · Sichuan, CN
• Xunyi Song · Hangzhou City, CN
• Hongming Gu · Chengdu, CN
• Youbiao Zou · Chengdu, CN
• Jinping Zhang · Grand Blanc, US
• Bo Zhang · Shanghai, CN

Key dates

• Filing date: Jun 29, 2016
• Grant date: Aug 21, 2018
• Expiry date: Jun 29, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/393
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting a P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least a P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting H+ ions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.