Patent · US Active

Semiconductor arrangement

US10056459B2 · kind B2 · utility

0Cited by

3References

9Claims

0Family size

Assignee

Nexperia B.V. · NL

Inventors

Thomas Igel-Holtzendorff · Nijmegen, NL
Reza Behtash · Hamburg, DE
Tim Boettcher · Scheeßel, DE

Key dates

Filing date	Oct 9, 2015
Grant date	Aug 21, 2018
Priority date	—
Expiry date	Oct 9, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/668
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor arrangement comprising a substrate having a first trench formed therein, a field plate layer arranged to extend within the first trench and coat the first trench, the field plate layer having a thickness such that it defines a second trench within the first trench, a barrier layer arranged to coat an internal surface of the second trench; and a trench fill material configured to substantially planarize the first and second trenches.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.