Methods for fabricating semiconductor device
US10056466B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2016 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Jun 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.