Field programmable gate array utilizing two-terminal non-volatile memory
US10056907B1 · kind B1 · utility
59Cited by
159References
20Claims
0Family size
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Key dates
| Filing date | May 12, 2017 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | May 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, coupling a second electrode of the first resistive element, and a first electrode of the second resistive element to a first terminal of a first transistor element, coupling a second terminal of the first transistor element to a first terminal of a latch, coupling a second terminal of the latch to a gate of a second transistor element, and coupling a gate of the first transistor element to a latch program signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.