Architecture and execution for efficient mixed precision computations in single instruction multiple data/thread (SIMD/T) devices
US10061592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2015 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Feb 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for improving power, performance, area (PPA) for mixed precision computations in a processing environment. The method includes determining a braiding factor as a number of units of work encoded into a physical thread. A value of the braiding factor is determined based on a mix of precision requirements presented for individual units of work. Units of work are classified as instructions for applied code transformation based on associated precision requirements for the processing environment. Instruction inputs from specified registers are packed together into a destination register according to the determined value of the braiding factor. The packed instructions presented in vector form are executed with an instruction set architecture configured for executing packed instructions of different precisions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.