Mitchell Alsup
43Patents
16h-index
37Co-inventors
81Inventor score
Filing activity: Nov 1, 1988 → Jul 22, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5355457A | Data processor for performing simultaneous instruction retirement and backtracking | Physics | 118 | Expired |
| US6976147B1 | Stride-based prefetch mechanism using a prediction confidence value | Physics | 93 | Expired |
| US5173617A | Digital phase lock clock generator without local oscillator | Electricity | 61 | Expired |
| US5367494A | Randomly accessible memory having time overlapping memory accesses | Physics | 50 | Expired |
| US7263600B2 | System and method for validating a memory file that links speculative results of load operations to register values | Physics | 49 | Expired |
| US4893267A | Method and apparatus for a data processor to support multi-mode, multi-precision integer arithmetic | Physics | 40 | Expired |
| US7003629B1 | System and method of identifying liveness groups within traces stored in a trace cache | Physics | 35 | Expired |
| US7613898B2 | Virtualizing an IOMMU | Physics | 34 | Active |
| US7315935B1 | Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots | Physics | 29 | Expired |
| US7548999B2 | Chained hybrid input/output memory management unit | Physics | 27 | Active |
| US7133969B2 | System and method for handling exceptional instructions in a trace cache based processor | Physics | 27 | Expired |
| US7133975B1 | Cache memory system including a cache memory employing a tag including associated touch bits | Physics | 26 | Expired |
| US5694564A | Data processing system a method for performing register renaming having back-up capability | Physics | 25 | Expired |
| US6950925B1 | Scheduler for use in a microprocessor that supports data-speculative execution | Physics | 23 | Expired |
| US7809923B2 | Direct memory access (DMA) address translation in an input/output memory management unit (IOMMU) | Physics | 20 | Active |
| US7552290B2 | Method for maintaining atomicity of instruction sequence to access a number of cache lines during proactive synchronization within a computer system | Physics | 18 | Active |
| US7197630B1 | Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation | Physics | 16 | Expired |
| US7653803B2 | Address translation for input/output (I/O) devices and interrupt remapping for I/O devices in an I/O memory management unit (IOMMU) | Physics | 10 | Active |
| US7073026B2 | Microprocessor including cache memory supporting multiple accesses per cycle | Physics | 9 | Expired |
| US7882330B2 | Virtualizing an IOMMU | Physics | 9 | Active |
| US7543131B2 | Controlling an I/O MMU | Physics | 9 | Active |
| US7043626B1 | Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming | Physics | 8 | Expired |
| US7480784B2 | Ensuring deadlock free operation for peer to peer traffic in an input/output memory management unit (IOMMU) | Physics | 7 | Active |
| US7636819B2 | Method for proactive synchronization within a computer system | Physics | 7 | Active |
| US7069411B1 | Mapper circuit with backup capability | Physics | 7 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.