Implementing random content of program loops in random test generation for processor verification
US10061672B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2013 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Apr 20, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for implementing random content of program loops in random test generation for processor verification. A converged branch instruction stream is used by a test generator to ensure that all random conditional branches converge to a main program loop. A built in exception handling mechanism of the test generator enables program interrupts to converge to the main program loop. Mandatory read only registers applied to the test generator allow all register based storage addresses to use registers that maintain a value and thus stabilize the storage address translations through subsequent iterations of the loop. A global class restriction mechanism defines specific restricted instruction classes applied to the test generator avoids inherently problematic operations for the program loops. Machine state detection and restoration mechanisms in the test generator are provided to preserve storage addressability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.