Olaf K. Hendrickson
9Patents
2h-index
16Co-inventors
44Inventor score
Filing activity: Mar 2, 2009 → Sep 23, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8275598B2 | Software table walk during test verification of a simulated densely threaded network on a chip | Physics | 5 | Active |
| US10061672B2 | Implementing random content of program loops in random test generation for processor verification | Physics | 4 | Active |
| US8918678B2 | Functional testing of a processor design | Physics | 0 | Active |
| US11443044B2 | Targeted very long delay for increasing speculative execution progression | Physics | 0 | Active |
| US11106602B2 | Memory blockade for verifying system security with respect to speculative execution | Physics | 0 | Active |
| US9720793B2 | Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads | Physics | 0 | Active |
| US11205005B2 | Identifying microarchitectural security vulnerabilities using simulation comparison with modified secret data | Physics | 0 | Active |
| US9251023B2 | Implementing automated memory address recording in constrained random test generation for verification of processor hardware designs | Physics | 0 | Active |
| US9734033B2 | Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.