Patent · US Active

Scalable multi-core system-on-chip architecture on multiple dice for high end microcontroller

US10061729B2 · kind B2 · utility

9Cited by

10References

25Claims

0Family size

Assignee

Ifineon Technologies AG · DE

Inventors

Albrecht Mayer · Deisenhofen, DE
Joerg Schepers · Rottach-Egern, DE
Frank Hellwig · Wunstorf, DE

Key dates

Filing date	Mar 19, 2018
Grant date	Aug 28, 2018
Priority date	—
Expiry date	Mar 19, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F15/7814
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.