Pattern weakness and strength detection and tracking during a semiconductor device fabrication process
US10062160B2 · kind B2 · utility
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24References
30Claims
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Key dates
| Filing date | Sep 20, 2017 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Sep 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.