System, apparatus and method for segmenting a memory array
US10062429B1 · kind B1 · utility
12Cited by
0References
20Claims
0Family size
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Key dates
| Filing date | Apr 17, 2017 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Apr 17, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.