Altug Koker
489Patents
14h-index
300Co-inventors
89Inventor score
Filing activity: Mar 17, 1999 → May 22, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10353706B2 | Instructions and logic to perform floating-point and integer operations for machine learning | Physics | 40 | Active |
| US10474458B2 | Instructions and logic to perform floating-point and integer operations for machine learning | Physics | 40 | Active |
| US11113784B2 | Sparse optimizations for a matrix accelerator architecture | Physics | 36 | Active |
| US11360767B2 | Instructions and logic to perform floating point and integer operations for machine learning | Physics | 33 | Active |
| US11080046B2 | Instructions and logic to perform floating point and integer operations for machine learning | Physics | 33 | Active |
| US11620256B2 | Systems and methods for improving cache efficiency and utilization | Physics | 32 | Active |
| US11169799B2 | Instructions and logic to perform floating-point and integer operations for machine learning | Physics | 31 | Active |
| US10186011B2 | Programmable coarse grained and sparse matrix compute hardware with advanced scheduling | Physics | 29 | Active |
| US10304154B2 | Coordination and increased utilization of graphics processors during inference | Emerging Cross-Sectional Technologies | 29 | Active |
| US10108850B1 | Recognition, reidentification and security enhancements using autonomous machines | Physics | 27 | Active |
| US10803548B2 | Disaggregation of SOC architecture | Emerging Cross-Sectional Technologies | 19 | Active |
| US9323684B2 | Dynamic cache and memory allocation for memory subsystems | Emerging Cross-Sectional Technologies | 18 | Active |
| US10380039B2 | Apparatus and method for memory management in a graphics processing environment | Physics | 17 | Active |
| US10332320B2 | Autonomous vehicle advanced sensing and response | Emerging Cross-Sectional Technologies | 16 | Active |
| US10043232B1 | Compute cluster preemption within a general-purpose graphics processing unit | Emerging Cross-Sectional Technologies | 13 | Active |
| US10062429B1 | System, apparatus and method for segmenting a memory array | Emerging Cross-Sectional Technologies | 12 | Active |
| US6457121B1 | Method and apparatus for reordering data in X86 ordering | Physics | 10 | Expired |
| US10401954B2 | Sensory enhanced augmented reality and virtual reality device | Physics | 10 | Active |
| US10282811B2 | Apparatus and method for managing data bias in a graphics processing architecture | Physics | 10 | Active |
| US7089367B1 | Reducing memory access latencies from a bus using pre-fetching and caching | Emerging Cross-Sectional Technologies | 8 | Expired |
| US10013734B1 | Programmable controller and command cache for graphics processors | Physics | 8 | Active |
| US11210760B2 | Programmable coarse grained and sparse matrix compute hardware with advanced scheduling | Physics | 7 | Active |
| US10242423B2 | Compute optimizations for low precision machine learning operations | Emerging Cross-Sectional Technologies | 7 | Active |
| US10102149B1 | Replacement policies for a hybrid hierarchical cache | Physics | 7 | Active |
| US10387160B2 | Shared local memory tiling mechanism | Physics | 6 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.